1. Field of the Invention
The present invention relates to a computer-implemented method for debugging low power circuit design in the field of integrated circuit (IC) design, and in particular, to a method for creating an integrated graphic user interface to debug the entire IC design including both logic circuit design and the associated low power network design.
2. Description of the Related Art
With the rapid progress of mobile devices and consumer electronic equipments during recent years, there are more applications such as smart cellular phones, personal mobile computers, MP3 audio players, notebooks and digital cameras to be presented to the public. As more functions and low power consumption are needed in thinner and lighter products, IC designers try to integrate varieties of discrete components on one chip to satisfy these requirements, which includes fewer components for a system design, lower production cost and smaller size of Printed Circuit Board (PCB). For example of a system-on-chip (SoC) design, it becomes more and more complex and harder to debug as more and more digital circuit design and low power network design are integrated into one chip. In many low power designs, a circuit design is divided into many parts and each part has a power supply, those parts are called power domains. In other words, power domain is a collection of instances, pins and ports that can share the same power distribution network (voltage). Some of the power domains can be turned on or off by a power switch. The main idea of using power switch is to turn off massive unused parts of the design and, as a result, conserve power consumption.
An isolation cell is used to isolate signals between two power domains where one is switched on and one is switched off. The most common usage of such cells is to isolate signals originating in a power domain that is being switched off, to the power domain that receives these signals and that remains switched on; an isolation cell ensures that when a power domain is turned off, its output will have some pre-defined or latched value, and this is why other active domains are not affected by turning some domains off.
In addition, a level shifter is required to change one voltage level into another voltage level across different power domains. Therefore, low power SoC design will contain not only pure digital circuits but also a sizeable power network with a plurality of power components controlled by control circuits.
Please refer to FIG. 1, digital circuit design is conventionally implemented in hardware description language (HDL), such as Verilog code 1. For the purpose of clarity, a term “power specification” is defined herein as the descriptions of the power intent (intended power behavior) on a circuit design. In order to implement low power network, the power description 2 specified in some power format such as Cadence Common Power Format (CPF) or Unified Power Format (UPF) is generally used to capture the low power information to allow designers to implement low power network design in a separate file without modifying the Verilog code 1. The power format is just a format to describe low power intent for design implementation, analysis and verification, and it is not limited to the CPF or UPF as long as it serves the low power design purpose.
In order to specify low power design constraints, it is required to specify a power supply network that can control the distribution of power so as to minimize energy consumption. Using UPF, one can easily specify the network at an abstract level. This network comprises supply ports, supply nets, and power switches, and is a high-level abstraction of the electrical network of the power aspect of the chip. Supply ports provide supply interfaces to power domains and switches, whereas supply nets connect supply ports. Since the supply network is specified apart from the logic design, the logic design specification remains independent of power supply network specifications.
Since traditional hardware description languages (HDL) are not adequate to specify the power design information, power format, such as UPF, provides a format without touching the existing HDL codes. For instance, UPF provides a command, create_power_domain, for creating a power domain and grouping the design instances belonging to the power domain. Other power components, such as power switches, isolation cells, and level shifters can be easily created by using the corresponding commands defined by power formats such as UPF.
Once the Verilog design and the power design based on the power format are taken into consideration, the entire IC design can be analyzed and subsequently a simulation to debug the IC design can be performed; but the visibility of the boundaries between power design and the pure digital design is low since there is no clear view to allow the designers to comprehend those boundaries in global view because it is required to visualize two separate text files to understand the relationship between the power network design and the circuit design; therefore designers have to dig into the massive Verilog code embedded with power components in the simulation database to debug the entire low power chip design.
Furthermore, circuit designers are mainly focusing on the functionalities of the circuit design, and hence they will build the hierarchies of the circuit design based on the functional and logic view. However, power designers will prefer to have the design hierarchies in physical form which can be defined by power format having a plurality of power domains within the power network design. As a result, it is inefficient and error prone for the designers to debug the entire chip if low power network design can not be viewed in the top level to interact with the power designer; therefore it is important to have a user graphic interface having the power network design in the top level while the associated digital design is viewable under power domains, so that the entire design can be viewed with main debugging focused on the power network design. In order to solve this problem, what is needed is a single integrated graphic user interface to view and debug the low power network with the associated digital circuit design which is regrouped and linked automatically under the power domains of the low power network, without requiring the designers to go back and forth between power specification codes and HDL codes to debug the design correctness between the low power network and the associated digital circuit across the entire chip.